Relative performance of multipliers: A fault tolerance perspective for parallel FFTs

As technology will increase as quality of circuits additionally will increase that tends face reliableness challenges and creates want for fault-tolerant implementations. Signal processing and communication circuits are effected by soft errors. The complexity increases as protection against soft errors increases in many applications. There are distinct advancements in VLSI technology i.e., number of circuits called Fast Fourier Transforms (FFTs) increased on a small chip. In this case we have to implement the fault tolerance in order to preserve the data efficiently. There are distinct techniques exist to achieve fault tolerance. The most used technique is algorithmic-primarily based fault tolerance (ABFT) techniques that attempt to use recursive properties to find and accurate errors. But in advanced systems it is not unusual that variety of the filters function in parallel, as an instance a filters having same response are connected in parallel and subjected to different inputs. ECC (error correction codes) is the one of the method to detect and correct errors in FFTs. We propose different multipliers in FFTs architecture for which multiplier is most suitable in whole design. In this proposed method each filter can be considered as a bit. This method allows most efficient protection when there is large number of parallel filters present. The method is evaluated employing a Array, changed booth, Wallace tree and Dadda multipliers showing the potency in terms of speed, low power consumption and space.