Diagnosis in modem design to volume the tip of the iceberg

The pain of debug, from 1 silicon to volume ramp Debug, especially in custom chip design (i.e.: microprocessors), many times seems to be more of a reactionary “fly by the seat of your pants” art than a “well thought out” tools-based procedure to solution. In fact, it is quite difficult to define tools to do 1 silicon debug since it seems each new problem is somehow specifically associated to some particular design facet or interaction of that facet with the particular silicon process you’re operating in.