An Energy Efficient SAR ADC Architecture with DAC Separation

A new SAR ADC architecture is proposed. The described circuit uses an additional low-resolution capacitive-DAC instead of MSB-capacitors switching in the conventional binary weighted DAC. The use of an additional DAC decreases the MSB capacitors size, therefore improves the energy efficiency and allows to achieve faster operation speed. The circuit operates using a 4-input comparator. The sampling capacitance is 98.4% reduced compared to conventional SAR ADC. The DAC switching energy saving of the proposed circuit is 97.2% compared to a conventional one. The 20 MS/s 10 bit SAR ADC based on the proposed architecture was simulated on transistor level. The power consumption and the Walden FOM are 70.88 uW and 3.71 fJ/conv.-step respectively.