{"title":"宽带数字控制16相变换器的设计与实现","authors":"X. Zhang, Y. Zhang, R. Zane, D. Maksimović","doi":"10.1109/COMPEL.2006.305660","DOIUrl":null,"url":null,"abstract":"In this paper we present design and implementation of a 16-phase digitally controlled converter with 1.56 MHz per-phase switching frequency, 25 MHz sampling rate, and the closed-loop bandwidth of approximately 1 MHz. The experimental system includes 16 buck converters, a digital multi-phase modulator and a digital controller implemented on an FPGA. Direct digital design of the compensator is based on a multi-level converter model. A preorder arrangement of phases is used to minimize the output ripple. A zero-error-bin approach addresses the effects of phase-mismatches and sub-harmonic ripples on the stability of the wide-bandwidth controller. Simulation and experimental results show that very wide bandwidth operation and very fast transient responses are feasible even in the presence of significant phase mismatches","PeriodicalId":210889,"journal":{"name":"2006 IEEE Workshops on Computers in Power Electronics","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2006-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":"{\"title\":\"Design and Implementation of a Wide-bandwidth Digitally Controlled 16-phase Converter\",\"authors\":\"X. Zhang, Y. Zhang, R. Zane, D. Maksimović\",\"doi\":\"10.1109/COMPEL.2006.305660\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper we present design and implementation of a 16-phase digitally controlled converter with 1.56 MHz per-phase switching frequency, 25 MHz sampling rate, and the closed-loop bandwidth of approximately 1 MHz. The experimental system includes 16 buck converters, a digital multi-phase modulator and a digital controller implemented on an FPGA. Direct digital design of the compensator is based on a multi-level converter model. A preorder arrangement of phases is used to minimize the output ripple. A zero-error-bin approach addresses the effects of phase-mismatches and sub-harmonic ripples on the stability of the wide-bandwidth controller. Simulation and experimental results show that very wide bandwidth operation and very fast transient responses are feasible even in the presence of significant phase mismatches\",\"PeriodicalId\":210889,\"journal\":{\"name\":\"2006 IEEE Workshops on Computers in Power Electronics\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-07-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"17\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE Workshops on Computers in Power Electronics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/COMPEL.2006.305660\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE Workshops on Computers in Power Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/COMPEL.2006.305660","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design and Implementation of a Wide-bandwidth Digitally Controlled 16-phase Converter
In this paper we present design and implementation of a 16-phase digitally controlled converter with 1.56 MHz per-phase switching frequency, 25 MHz sampling rate, and the closed-loop bandwidth of approximately 1 MHz. The experimental system includes 16 buck converters, a digital multi-phase modulator and a digital controller implemented on an FPGA. Direct digital design of the compensator is based on a multi-level converter model. A preorder arrangement of phases is used to minimize the output ripple. A zero-error-bin approach addresses the effects of phase-mismatches and sub-harmonic ripples on the stability of the wide-bandwidth controller. Simulation and experimental results show that very wide bandwidth operation and very fast transient responses are feasible even in the presence of significant phase mismatches
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
