{"title":"采用65nm CMOS工艺的35GHz高带宽全集成单片FMCW雷达收发器","authors":"Chen Zhao, Yuan Chen, Xinyi Sheng, Bowen Ding, S. Yuan, Tong Tian","doi":"10.1109/APMC.2015.7411588","DOIUrl":null,"url":null,"abstract":"A fully integrated 35GHz linearly Frequency Modulated Continuous Wave (FMCW) single-chip radar transceiver is successfully implemented in 65nm standard CMOS process. The single-chip transceiver is configured in one transmitter and two receivers and includes a wideband process-oriented optimized QVCO, a mm-Wave power amplifier, low noise amplifiers, low noise passive mixers, IF amplifiers as well as control blocks and power management blocks. The one-transmitter-two-receiver configuration will help the radar provide additional functions such as direction angle detecting, positioning and so on. Specially developed design and modeling technologies are involved to promote the linearity and phase noise level of the transmitting link and noise performance of the receiving links. Furthermore, the chip is designed in modularity and presents possibilities with chips to compose MIMO, Phase Array system or other specific detecting system. The presented single chip radar transceiver is able to provide 10dBm output power with 1.5GHz frequency sweep range, 12dB single side band noise figure and draw 170mA current from 1.2V supply.","PeriodicalId":269888,"journal":{"name":"2015 Asia-Pacific Microwave Conference (APMC)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A fully integrated single-chip 35GHz FMCW radar transceiver with high bandwidth in 65nm CMOS process\",\"authors\":\"Chen Zhao, Yuan Chen, Xinyi Sheng, Bowen Ding, S. Yuan, Tong Tian\",\"doi\":\"10.1109/APMC.2015.7411588\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A fully integrated 35GHz linearly Frequency Modulated Continuous Wave (FMCW) single-chip radar transceiver is successfully implemented in 65nm standard CMOS process. The single-chip transceiver is configured in one transmitter and two receivers and includes a wideband process-oriented optimized QVCO, a mm-Wave power amplifier, low noise amplifiers, low noise passive mixers, IF amplifiers as well as control blocks and power management blocks. The one-transmitter-two-receiver configuration will help the radar provide additional functions such as direction angle detecting, positioning and so on. Specially developed design and modeling technologies are involved to promote the linearity and phase noise level of the transmitting link and noise performance of the receiving links. Furthermore, the chip is designed in modularity and presents possibilities with chips to compose MIMO, Phase Array system or other specific detecting system. The presented single chip radar transceiver is able to provide 10dBm output power with 1.5GHz frequency sweep range, 12dB single side band noise figure and draw 170mA current from 1.2V supply.\",\"PeriodicalId\":269888,\"journal\":{\"name\":\"2015 Asia-Pacific Microwave Conference (APMC)\",\"volume\":\"88 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 Asia-Pacific Microwave Conference (APMC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APMC.2015.7411588\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 Asia-Pacific Microwave Conference (APMC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APMC.2015.7411588","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A fully integrated single-chip 35GHz FMCW radar transceiver with high bandwidth in 65nm CMOS process
A fully integrated 35GHz linearly Frequency Modulated Continuous Wave (FMCW) single-chip radar transceiver is successfully implemented in 65nm standard CMOS process. The single-chip transceiver is configured in one transmitter and two receivers and includes a wideband process-oriented optimized QVCO, a mm-Wave power amplifier, low noise amplifiers, low noise passive mixers, IF amplifiers as well as control blocks and power management blocks. The one-transmitter-two-receiver configuration will help the radar provide additional functions such as direction angle detecting, positioning and so on. Specially developed design and modeling technologies are involved to promote the linearity and phase noise level of the transmitting link and noise performance of the receiving links. Furthermore, the chip is designed in modularity and presents possibilities with chips to compose MIMO, Phase Array system or other specific detecting system. The presented single chip radar transceiver is able to provide 10dBm output power with 1.5GHz frequency sweep range, 12dB single side band noise figure and draw 170mA current from 1.2V supply.