{"title":"IEEE-488/1978接口芯片的硬件设计","authors":"L. Spaanenburg, G. Kaat, A. Kooy","doi":"10.1109/ESSCIRC.1980.5468791","DOIUrl":null,"url":null,"abstract":"A random-logic integrated realization of the IEEE-488/1978 standard interface is discussed. Techniques are shown to optimize the logic design as well as the testability.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Hardware Design for an IEEE-488/1978 Interface Chip\",\"authors\":\"L. Spaanenburg, G. Kaat, A. Kooy\",\"doi\":\"10.1109/ESSCIRC.1980.5468791\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A random-logic integrated realization of the IEEE-488/1978 standard interface is discussed. Techniques are shown to optimize the logic design as well as the testability.\",\"PeriodicalId\":168272,\"journal\":{\"name\":\"ESSCIRC 80: 6th European Solid State Circuits Conference\",\"volume\":\"37 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1980-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 80: 6th European Solid State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.1980.5468791\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 80: 6th European Solid State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.1980.5468791","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Hardware Design for an IEEE-488/1978 Interface Chip
A random-logic integrated realization of the IEEE-488/1978 standard interface is discussed. Techniques are shown to optimize the logic design as well as the testability.
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