一个0.7- 1gb /s的CMOS时钟恢复电路

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) Pub Date : 1999-08-23 DOI:10.1109/APASIC.1999.824086

Hui Wang, R. Nottenburg

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引用次数: 1

摘要

利用0.5 /spl mu/m的数字CMOS工艺，设计了一个0.7 ~ 1gb /s的时钟恢复电路。它由一个用于锁频的砰砰式鉴频器(FD)和一个用于锁相的线性鉴相器(PD)组成。FD能够在频率锁定时自行复位。恢复时钟的测量有效值抖动在1ghz时为7.4 ps，在0.7 GHz时为7 ps。它能够维持一个比10/sup -11/更好的误码率高达140个缺失转换。它的功耗为200mw，电源为5v。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 0.7-1 Gb/s CMOS clock recovery circuit

A 0.7-1 Gb/s clock recovery circuit is designed by ruing a 0.5 /spl mu/m digital CMOS process. It consists of a bang-bang type frequency detector (FD) to acquire frequency lock and a linear phase detector (PD) to acquire phase lock. The FD is able to reset itself upon frequency lock. Measured RMS jitter of the recovered clock is 7.4 ps at 1 GHz and 7 ps at 0.7 GHz. It is able to maintain a BER better than 10/sup -11/ for up to 140 missing transitions. It consumes 200 mW with a 5 V power supply.

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AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)

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