4Gb/s/引脚4级同步双向I/O，使用500MHz时钟用于高速内存

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI:10.1109/ISSCC.2004.1332687

Jin-Hyun Kim, Sua Kim, Woo-Seop Kim, J. Choi, H. Hwang, Changhyun Kim, Sooin Cho, Suki Kim

{"title":"4Gb/s/引脚4级同步双向I/O，使用500MHz时钟用于高速内存","authors":"Jin-Hyun Kim, Sua Kim, Woo-Seop Kim, J. Choi, H. Hwang, Changhyun Kim, Sooin Cho, Suki Kim","doi":"10.1109/ISSCC.2004.1332687","DOIUrl":null,"url":null,"abstract":"A simultaneous 4-level bidirectional I/O interface for high-speed DRAM is presented. It performs at a data rate of 4Gb/s/pin with the use of a 500MHz clock generator and a full CMOS power rail swing. This I/O interface is fabricated on a 0.10/spl mu/m DRAM CMOS process in 330x66/spl mu/m/sup 2/. The transceiver performs 200mVx690ps passing eye-windows on the channel over 1.8V supply.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A 4Gb/s/pin 4-level simultaneous bidirectional I/O using a 500MHz clock for high-speed memory\",\"authors\":\"Jin-Hyun Kim, Sua Kim, Woo-Seop Kim, J. Choi, H. Hwang, Changhyun Kim, Sooin Cho, Suki Kim\",\"doi\":\"10.1109/ISSCC.2004.1332687\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A simultaneous 4-level bidirectional I/O interface for high-speed DRAM is presented. It performs at a data rate of 4Gb/s/pin with the use of a 500MHz clock generator and a full CMOS power rail swing. This I/O interface is fabricated on a 0.10/spl mu/m DRAM CMOS process in 330x66/spl mu/m/sup 2/. The transceiver performs 200mVx690ps passing eye-windows on the channel over 1.8V supply.\",\"PeriodicalId\":273317,\"journal\":{\"name\":\"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-09-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2004.1332687\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2004.1332687","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 6

摘要

提出了一种用于高速DRAM的同时4级双向I/O接口。它的数据速率为4Gb/s/引脚，使用500MHz时钟发生器和全CMOS电源导轨摆幅。这个I/O接口是在330x66/spl mu/m/sup 2/ /的0.10/spl mu/m DRAM CMOS工艺上制造的。收发器在1.8V供电的通道上执行200mVx690ps通过眼窗。

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A 4Gb/s/pin 4-level simultaneous bidirectional I/O using a 500MHz clock for high-speed memory

A simultaneous 4-level bidirectional I/O interface for high-speed DRAM is presented. It performs at a data rate of 4Gb/s/pin with the use of a 500MHz clock generator and a full CMOS power rail swing. This I/O interface is fabricated on a 0.10/spl mu/m DRAM CMOS process in 330x66/spl mu/m/sup 2/. The transceiver performs 200mVx690ps passing eye-windows on the channel over 1.8V supply.

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2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

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