{"title":"数字锁延环混合DPWM","authors":"V. Yousefzadeh, T. Takayama, D. Maksimović","doi":"10.1109/COMPEL.2006.305666","DOIUrl":null,"url":null,"abstract":"This paper introduces a fully synthesizable hybrid digital pulse width modulator (DPWM). The DPWM includes a digital delay locked loop around a delay-line with discretely programmable delay cells to achieve constant-frequency clocked operation with the best possible resolution over a range of process or temperature variations. The DPWM module can implement trailing-edge, leading-edge or triangular modulation. It includes two outputs with programmable dead-times, suitable for DC-DC converters with synchronous rectifiers. The DPWM module is well suited for FPGA or custom chip implementation. Experimental results are shown for a 780 KHz, 10-bit FPGA realization","PeriodicalId":210889,"journal":{"name":"2006 IEEE Workshops on Computers in Power Electronics","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2006-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"123","resultStr":"{\"title\":\"Hybrid DPWM with Digital Delay-Locked Loop\",\"authors\":\"V. Yousefzadeh, T. Takayama, D. Maksimović\",\"doi\":\"10.1109/COMPEL.2006.305666\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper introduces a fully synthesizable hybrid digital pulse width modulator (DPWM). The DPWM includes a digital delay locked loop around a delay-line with discretely programmable delay cells to achieve constant-frequency clocked operation with the best possible resolution over a range of process or temperature variations. The DPWM module can implement trailing-edge, leading-edge or triangular modulation. It includes two outputs with programmable dead-times, suitable for DC-DC converters with synchronous rectifiers. The DPWM module is well suited for FPGA or custom chip implementation. Experimental results are shown for a 780 KHz, 10-bit FPGA realization\",\"PeriodicalId\":210889,\"journal\":{\"name\":\"2006 IEEE Workshops on Computers in Power Electronics\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-07-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"123\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE Workshops on Computers in Power Electronics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/COMPEL.2006.305666\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE Workshops on Computers in Power Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/COMPEL.2006.305666","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper introduces a fully synthesizable hybrid digital pulse width modulator (DPWM). The DPWM includes a digital delay locked loop around a delay-line with discretely programmable delay cells to achieve constant-frequency clocked operation with the best possible resolution over a range of process or temperature variations. The DPWM module can implement trailing-edge, leading-edge or triangular modulation. It includes two outputs with programmable dead-times, suitable for DC-DC converters with synchronous rectifiers. The DPWM module is well suited for FPGA or custom chip implementation. Experimental results are shown for a 780 KHz, 10-bit FPGA realization