Investigation and design of the efficient hardware-based RNG for cryptographic applications

The best security factor in any encryption algorithm is the random values used in key management or the structure of the algorithm itself. Thus, some of the encryption algorithm employed random number generator to produce this type of numbers. This paper describes the process of selecting the most efficient algorithm to represent the hardware RNG for the usage in cryptography. For this purpose, a number of RNG algorithms are selected and analyzed in terms of the sequence's randomness using theoretical simulator analysis. Among of the algorithms, the Inverse Congruential Generator algorithm was chosen based on the analysis as it provides the most high quality random sequence and insensitivity in initial condition. The algorithm was further proceed to the NIST test for non-randomness test and it shown reasonable complexity. The design was proven to be implemented successfully on hardware as it then been designed using Verilog HDL and been simulated and verified using Altera QuartusII 9.0sp2 web edition software. The design utilized 7,711 logic elements of Cyclone EP1C20F400C6. Benefited the usage of FPGA, the design could possibly provide reduction in size of the RNG, low power consumption and low cost production for hardware-based encryption.