Multi-technique study of defect generation in high-k gate stacks

A set of measurement techniques- SILC, low frequency noise, and pulse CV - combined with the physical descriptions of the processes associated with these measurements were applied to study pre-existing and stress generated traps in the SiO2/HfO2 gate stacks. By correlating the analysis results obtained by these techniques, the defects in the high-k dielectric and interfacial layer were identified. The stress-induced degradation of the high-k gate stack was found to be caused primarily by the trap generation in the SiO2 interfacial layer.