高度可制造的4gb DRAM采用0.11 /spl mu/m DRAM技术

International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138) Pub Date : 2000-12-10 DOI:10.1109/IEDM.2000.904328

H. Jeong, W.S. Yang, Y. Hwang, C. Cho, S. Park, S. Ahn, Y. Chun, S. shin, S.H. Song, J.Y. Lee, S. Jang, C.H. Lee, J. Jeong, M. Cho, J.K. Lee, Kinam Kim

{"title":"高度可制造的4gb DRAM采用0.11 /spl mu/m DRAM技术","authors":"H. Jeong, W.S. Yang, Y. Hwang, C. Cho, S. Park, S. Ahn, Y. Chun, S. shin, S.H. Song, J.Y. Lee, S. Jang, C.H. Lee, J. Jeong, M. Cho, J.K. Lee, Kinam Kim","doi":"10.1109/IEDM.2000.904328","DOIUrl":null,"url":null,"abstract":"4 Gb DRAM has been developed successfully using 0.11 /spl mu/m DRAM technology. Considering manufacturability, we have focused on developing patterning technology that makes 0.11 /spl mu/m design rules possible using KrF lithography. Also, novel DRAM technologies, which have a big influence on the future DRAM integration, are developed as follows:, using novel oxide (SOG) for the enhanced capability of gap-filling, borderless metal contact and stud processes, line-type storage node SAC, thin gate oxide, and CVD Al process for metal interconnections.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"Highly manufacturable 4 Gb DRAM using using 0.11 /spl mu/m DRAM technology\",\"authors\":\"H. Jeong, W.S. Yang, Y. Hwang, C. Cho, S. Park, S. Ahn, Y. Chun, S. shin, S.H. Song, J.Y. Lee, S. Jang, C.H. Lee, J. Jeong, M. Cho, J.K. Lee, Kinam Kim\",\"doi\":\"10.1109/IEDM.2000.904328\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"4 Gb DRAM has been developed successfully using 0.11 /spl mu/m DRAM technology. Considering manufacturability, we have focused on developing patterning technology that makes 0.11 /spl mu/m design rules possible using KrF lithography. Also, novel DRAM technologies, which have a big influence on the future DRAM integration, are developed as follows:, using novel oxide (SOG) for the enhanced capability of gap-filling, borderless metal contact and stud processes, line-type storage node SAC, thin gate oxide, and CVD Al process for metal interconnections.\",\"PeriodicalId\":276800,\"journal\":{\"name\":\"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-12-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2000.904328\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2000.904328","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 11

摘要

采用0.11 /spl mu/m DRAM技术成功开发了4gb DRAM。考虑到可制造性，我们专注于开发图案技术，使用KrF光刻技术使0.11 /spl mu/m设计规则成为可能。此外，对未来DRAM集成化有重大影响的新DRAM技术有:使用新型氧化物(SOG)增强间隙填充能力，无边界金属接触和螺栓工艺，线型存储节点SAC，薄栅氧化物和CVD Al工艺用于金属互连。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

Highly manufacturable 4 Gb DRAM using using 0.11 /spl mu/m DRAM technology

4 Gb DRAM has been developed successfully using 0.11 /spl mu/m DRAM technology. Considering manufacturability, we have focused on developing patterning technology that makes 0.11 /spl mu/m design rules possible using KrF lithography. Also, novel DRAM technologies, which have a big influence on the future DRAM integration, are developed as follows:, using novel oxide (SOG) for the enhanced capability of gap-filling, borderless metal contact and stud processes, line-type storage node SAC, thin gate oxide, and CVD Al process for metal interconnections.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)

自引率

0.00%

发文量