M. H. Lee, Sheng-Ting Fan, C.-H. Tang, P. Chen, Y.-C. Chou, H. Chen, J. Kuo, M. Xie, S.-N. Liu, M. Liao, C. Jong, K.-S. Li, M.-C. Chen, C. Liu
{"title":"物理厚度xnm铁电HfZrOx负电容场效应管","authors":"M. H. Lee, Sheng-Ting Fan, C.-H. Tang, P. Chen, Y.-C. Chou, H. Chen, J. Kuo, M. Xie, S.-N. Liu, M. Liao, C. Jong, K.-S. Li, M.-C. Chen, C. Liu","doi":"10.1109/IEDM.2016.7838400","DOIUrl":null,"url":null,"abstract":"Ferroelectric HfZrOx (FE-HZO) negative capacitance (NC) FETs is experimentally demonstrated with physical thickness 1.5 nm, SS = 52 mV/dec, hysteresis free (threshold voltage shift = 0.8 mV), and 0.65 nm CET (capacitance equivalent thickness). The NC-FinFET modeling is validated on standard 14nm FinFET. The transient behavior of gate and drain current response are exhibited with triangular gate voltage sweep. The dynamic NC model with compact equivalent circuit for ultra-thin FE-HZO is established with experimental data validation, and estimates the fast response. A feasible concept of coupling the ultra-thin FE-HZO (1.x nm) with NC as gate stack paves a promising solution for sub-10nm technology node.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"111","resultStr":"{\"title\":\"Physical thickness 1.x nm ferroelectric HfZrOx negative capacitance FETs\",\"authors\":\"M. H. Lee, Sheng-Ting Fan, C.-H. Tang, P. Chen, Y.-C. Chou, H. Chen, J. Kuo, M. Xie, S.-N. Liu, M. Liao, C. Jong, K.-S. Li, M.-C. Chen, C. Liu\",\"doi\":\"10.1109/IEDM.2016.7838400\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Ferroelectric HfZrOx (FE-HZO) negative capacitance (NC) FETs is experimentally demonstrated with physical thickness 1.5 nm, SS = 52 mV/dec, hysteresis free (threshold voltage shift = 0.8 mV), and 0.65 nm CET (capacitance equivalent thickness). The NC-FinFET modeling is validated on standard 14nm FinFET. The transient behavior of gate and drain current response are exhibited with triangular gate voltage sweep. The dynamic NC model with compact equivalent circuit for ultra-thin FE-HZO is established with experimental data validation, and estimates the fast response. A feasible concept of coupling the ultra-thin FE-HZO (1.x nm) with NC as gate stack paves a promising solution for sub-10nm technology node.\",\"PeriodicalId\":186544,\"journal\":{\"name\":\"2016 IEEE International Electron Devices Meeting (IEDM)\",\"volume\":\"2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"111\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE International Electron Devices Meeting (IEDM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2016.7838400\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Electron Devices Meeting (IEDM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2016.7838400","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Ferroelectric HfZrOx (FE-HZO) negative capacitance (NC) FETs is experimentally demonstrated with physical thickness 1.5 nm, SS = 52 mV/dec, hysteresis free (threshold voltage shift = 0.8 mV), and 0.65 nm CET (capacitance equivalent thickness). The NC-FinFET modeling is validated on standard 14nm FinFET. The transient behavior of gate and drain current response are exhibited with triangular gate voltage sweep. The dynamic NC model with compact equivalent circuit for ultra-thin FE-HZO is established with experimental data validation, and estimates the fast response. A feasible concept of coupling the ultra-thin FE-HZO (1.x nm) with NC as gate stack paves a promising solution for sub-10nm technology node.