{"title":"亚100纳米嵌入式SRAM设计的vth变化分析","authors":"M. Yamaoka, H. Onodera","doi":"10.1109/SOCC.2006.283905","DOIUrl":null,"url":null,"abstract":"A Vth variation has large impact on SRAM operation. To predict an SRAM operating margin in design phase, a Vth window analysis is used. We propose an improved Vth window analysis, which considers a relationship between global and local Vth variation, and the analysis enables accurate operating margin prediction. This analysis predicts 7.7% larger yield deterioration than conventional method in 65-nm manufacturing process and gives a chance to introduce some operating margin enhancement circuits in design phase.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"A Detailed Vth-Variation Analysis for Sub-100-nm Embedded SRAM Design\",\"authors\":\"M. Yamaoka, H. Onodera\",\"doi\":\"10.1109/SOCC.2006.283905\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A Vth variation has large impact on SRAM operation. To predict an SRAM operating margin in design phase, a Vth window analysis is used. We propose an improved Vth window analysis, which considers a relationship between global and local Vth variation, and the analysis enables accurate operating margin prediction. This analysis predicts 7.7% larger yield deterioration than conventional method in 65-nm manufacturing process and gives a chance to introduce some operating margin enhancement circuits in design phase.\",\"PeriodicalId\":345714,\"journal\":{\"name\":\"2006 IEEE International SOC Conference\",\"volume\":\"33 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE International SOC Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCC.2006.283905\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE International SOC Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC.2006.283905","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Detailed Vth-Variation Analysis for Sub-100-nm Embedded SRAM Design
A Vth variation has large impact on SRAM operation. To predict an SRAM operating margin in design phase, a Vth window analysis is used. We propose an improved Vth window analysis, which considers a relationship between global and local Vth variation, and the analysis enables accurate operating margin prediction. This analysis predicts 7.7% larger yield deterioration than conventional method in 65-nm manufacturing process and gives a chance to introduce some operating margin enhancement circuits in design phase.
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