基于28nm数字CMOS的70db SNDR 200ms /s 2.3 mW动态流水线SAR ADC

2014 Symposium on VLSI Circuits Digest of Technical Papers Pub Date : 2014-06-10 DOI:10.1109/VLSIC.2014.6858451

B. Verbruggen, K. Deguchi, Badr Malki, J. Craninckx

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引用次数: 81

摘要

提出了一种基于28nm数字CMOS的200 MS/s 2倍交叉14位流水线SAR ADC。该ADC采用了一种新型残留放大器，在低功耗下实现低噪声，并结合了交错通道时间常数校准。该ADC在200 MS/s时的峰值SNDR为70.7 dB，同时从0.9 V电源消耗2.3 mW。

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A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOS

We present a 200 MS/s 2x interleaved 14 bit pipelined SAR ADC in 28nm digital CMOS. The ADC uses a new residue amplifier for low noise at low power, and incorporates interleaved channel time-constant calibration. The ADC achieves a peak SNDR of 70.7 dB at 200 MS/s while consuming 2.3 mW from an 0.9 V supply.

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2014 Symposium on VLSI Circuits Digest of Technical Papers

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