{"title":"一个750ks /s的8位低功耗流水线A/D转换器","authors":"V. Valencic, P. Deval","doi":"10.1109/ESSCIRC.1988.5468461","DOIUrl":null,"url":null,"abstract":"A switched-capacitor pipelined A/D convertor is described, in which the amplifier offset compensation is inherent to the circuit structure and the effect of clock-feedthrough is as low as 0.5 mV. Preliminary experimental results, obtained on circuits fabricated using a low-voltage CMOS technology, indicate 8- bit resolution for 750 kHz sampling frequency, with only 5 mW power consumption.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A 750 ks/s 8-Bit Low-Power Pipelined A/D Converter\",\"authors\":\"V. Valencic, P. Deval\",\"doi\":\"10.1109/ESSCIRC.1988.5468461\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A switched-capacitor pipelined A/D convertor is described, in which the amplifier offset compensation is inherent to the circuit structure and the effect of clock-feedthrough is as low as 0.5 mV. Preliminary experimental results, obtained on circuits fabricated using a low-voltage CMOS technology, indicate 8- bit resolution for 750 kHz sampling frequency, with only 5 mW power consumption.\",\"PeriodicalId\":197244,\"journal\":{\"name\":\"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.1988.5468461\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.1988.5468461","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 750 ks/s 8-Bit Low-Power Pipelined A/D Converter
A switched-capacitor pipelined A/D convertor is described, in which the amplifier offset compensation is inherent to the circuit structure and the effect of clock-feedthrough is as low as 0.5 mV. Preliminary experimental results, obtained on circuits fabricated using a low-voltage CMOS technology, indicate 8- bit resolution for 750 kHz sampling frequency, with only 5 mW power consumption.
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