{"title":"用于DVB-S2/S2X/T2的改进型最小和LDPC解码器","authors":"Fady Tadros, S. Eisa, H. Issa, K. Shehata","doi":"10.1109/ICM.2018.8704096","DOIUrl":null,"url":null,"abstract":"Min sum algorithm (MSA) is widely used for decoding Low Density Parity Check (LDPC) codes in many modern Digital Video Broadcasting (DVB) as a simplification for Sum Product Algorithm (SPA) which greatly reduce the implementation complexity. This paper presents a design of modified variable scaling min sum LDPC decoding algorithm for DVB-S2/S2X/T2. The proposed design is a combination between the variable Normalized Min Sum Algorithm (NMSA) and the Offset Min Sum Algorithm (OMSA) which provides a trade-off between decoding complexity and error correcting performance. It improves the use of the Min Sum Algorithm (MSA) by 39%. A proposal for how to implement the proposed algorithm using FPGA is also introduced. The structure used is partially parallel layered decoder architecture.","PeriodicalId":305356,"journal":{"name":"2018 30th International Conference on Microelectronics (ICM)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Modified Scaled Min Sum LDPC Decoder for DVB-S2/S2X/T2\",\"authors\":\"Fady Tadros, S. Eisa, H. Issa, K. Shehata\",\"doi\":\"10.1109/ICM.2018.8704096\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Min sum algorithm (MSA) is widely used for decoding Low Density Parity Check (LDPC) codes in many modern Digital Video Broadcasting (DVB) as a simplification for Sum Product Algorithm (SPA) which greatly reduce the implementation complexity. This paper presents a design of modified variable scaling min sum LDPC decoding algorithm for DVB-S2/S2X/T2. The proposed design is a combination between the variable Normalized Min Sum Algorithm (NMSA) and the Offset Min Sum Algorithm (OMSA) which provides a trade-off between decoding complexity and error correcting performance. It improves the use of the Min Sum Algorithm (MSA) by 39%. A proposal for how to implement the proposed algorithm using FPGA is also introduced. The structure used is partially parallel layered decoder architecture.\",\"PeriodicalId\":305356,\"journal\":{\"name\":\"2018 30th International Conference on Microelectronics (ICM)\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 30th International Conference on Microelectronics (ICM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICM.2018.8704096\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 30th International Conference on Microelectronics (ICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICM.2018.8704096","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Modified Scaled Min Sum LDPC Decoder for DVB-S2/S2X/T2
Min sum algorithm (MSA) is widely used for decoding Low Density Parity Check (LDPC) codes in many modern Digital Video Broadcasting (DVB) as a simplification for Sum Product Algorithm (SPA) which greatly reduce the implementation complexity. This paper presents a design of modified variable scaling min sum LDPC decoding algorithm for DVB-S2/S2X/T2. The proposed design is a combination between the variable Normalized Min Sum Algorithm (NMSA) and the Offset Min Sum Algorithm (OMSA) which provides a trade-off between decoding complexity and error correcting performance. It improves the use of the Min Sum Algorithm (MSA) by 39%. A proposal for how to implement the proposed algorithm using FPGA is also introduced. The structure used is partially parallel layered decoder architecture.