基于改进时钟的BIST低功耗测试图发生器

Bharti Moryani, D. Mishra
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引用次数: 4

摘要

随着技术的进步,电池供电设备对长寿命电池的需求不断增长,为降低这些设备的功耗开辟了新思路。我们知道,在测试过程中,当设备的正常工作模式关闭时,功率的耗散比正常工作模式大约多200%。为此,提出了一种从一开始就使测试模式本身的相关功率最小的方法。本文提出了一种新的测试电路的“测试图发生器”设计。作者提出了一种不同于目前使用的LFSR的设计方案。这里提出的测试模式生成器涉及到使用一个灰色码生成器和一个修改的时钟方案。电路作为一个整体将产生两个连续集之间的汉明距离为1的穷举测试模式集。这种逻辑背后的想法是最小化动态功耗,这是由于晶体管在闸级的开关活动增加而发生的。修改后的时钟将仅为逻辑从0到1或从1到0变化的触发器激活时钟。采用这种设计获得的功率约为36兆瓦。
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Low power test pattern generator with modified clock for BIST
As technology progresses, the growing demands of long life batteries in battery operated devices have set ways for new ideas that reduce the power consumed in these devices. As we know that during testing when the device's normal functioning mode is off, the dissipation of power is approximately 200% more than that of normal functioning mode. So a method is proposed to minimize the concerned power at testing mode itself in the very beginning. This paper proposes a new design of “Test Pattern generator” for testing the circuits. The author has proposed a design which is quite different from the LFSR used till now. The test pattern generator proposed here has involved the use of a gray code generator together with a modified clock scheme. The circuit as a whole will generate exhaustive set of test patterns with hamming distance of one in between two consecutive sets. The idea behind this logic is to minimize dynamic power consumption which occurs because of increase in switching activity of the transistors at gate level. The modified clock will activate the clock only for that flip-flop where the logic changes from 0 to 1 or from 1 to 0. The power obtained using this design is about 36 mw.
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