A low-power, medium-resolution, high-speed CMOS pipelined ADC

This paper presents the systematic design approach of a low-power, medium-resolution, high-speed pipelined Analog-to-Digital Converter (ADC). The ADC is implemented in 180nm digital CMOS technology. The converter achieves signal-to-noise distortion ratio of 59.8 dB, spurious-free dynamic range of 89 dB and effective number of bits of 9.64-bits at sampling speed of 50MHz with an input signal frequency of 4MHz. The peak differential-nonlinearity of the converter is 0.28/−0.17LSB and integral-nonlinearity of the converter is +0.42/−0.41LSB. The proposed 10-bit, 50MS/sec pipelined ADC consumes 24.5mW amount of power from 1.8V supply.