Synthesis of self-timed FIFO circuit from signal transition graphs (STGs)

As we build faster digital switching circuits, the ability to accomplish global synchronization with a high-speed clock becomes a limiting factor to system throughput. Self-timed circuit design is an active research area and synthesis of self-timed control circuits using signal transition graphs is a promising approach. Our goal is to construct a FIFO circuit that does not require the distribution of a clocking signal. We use the notation of signal transition graphs to describe circuit behavior. Since circuit behavior is presented by signal transitions rather than states, signal transition graphs simplify the algorithm and graph manipulation. The synthesized logic is hazard-free and guaranteed to have the fastest operation compared with similar designs.