{"title":"三种ATM专用集成电路的设计与仿真","authors":"Chan Kim, J. Jun, Sang Ho Lee, Jae Geun Kim","doi":"10.1109/APASIC.1999.824019","DOIUrl":null,"url":null,"abstract":"In ASIC development, effective simulation leads into functionally more reliable chips as well as faster development time. This paper describes the design and the simulation techniques used in 3 ATM ASIC developments in ETRI. The three ASICs described are: ASAH-NIC-a 155 Mbps ATM SAR chip with internal PCI interface and SDH framer; ASAPI-L4-a 622 Mbps bidirectional ATM layer processing chip with UPC, OAM, QOS buffering capabilities; and ASAH-P4-a 622 Mbps ATM physical layer chip.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design and simulation of three ATM ASICs\",\"authors\":\"Chan Kim, J. Jun, Sang Ho Lee, Jae Geun Kim\",\"doi\":\"10.1109/APASIC.1999.824019\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In ASIC development, effective simulation leads into functionally more reliable chips as well as faster development time. This paper describes the design and the simulation techniques used in 3 ATM ASIC developments in ETRI. The three ASICs described are: ASAH-NIC-a 155 Mbps ATM SAR chip with internal PCI interface and SDH framer; ASAPI-L4-a 622 Mbps bidirectional ATM layer processing chip with UPC, OAM, QOS buffering capabilities; and ASAH-P4-a 622 Mbps ATM physical layer chip.\",\"PeriodicalId\":346808,\"journal\":{\"name\":\"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-08-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APASIC.1999.824019\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APASIC.1999.824019","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In ASIC development, effective simulation leads into functionally more reliable chips as well as faster development time. This paper describes the design and the simulation techniques used in 3 ATM ASIC developments in ETRI. The three ASICs described are: ASAH-NIC-a 155 Mbps ATM SAR chip with internal PCI interface and SDH framer; ASAPI-L4-a 622 Mbps bidirectional ATM layer processing chip with UPC, OAM, QOS buffering capabilities; and ASAH-P4-a 622 Mbps ATM physical layer chip.
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