{"title":"系统级封装(SiP)实现平台的电气和热分析","authors":"Michael X. Wang, Katsuharu Suzuki, W. Dai","doi":"10.1109/ISQED.2003.1194736","DOIUrl":null,"url":null,"abstract":"This paper presents an electrical and thermal performance analysis of system-in-a-package (SiP) memory/logic implementation platform based on chip-laminate-chip (CLC) technology. Internal IO interface inside CLC module has been modeled and compared with stack-chip (SC) implementation. Thermal analysis, including comparison against stack-chip and system-on- a-chip (SoC) is also presented. It is demonstrated that CLC technology provides significant performance advantage over conventional SiP technologies and has great impact on future system-level integration.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Electrical and thermal analysis for system-in-a package (SiP) implementation platform\",\"authors\":\"Michael X. Wang, Katsuharu Suzuki, W. Dai\",\"doi\":\"10.1109/ISQED.2003.1194736\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents an electrical and thermal performance analysis of system-in-a-package (SiP) memory/logic implementation platform based on chip-laminate-chip (CLC) technology. Internal IO interface inside CLC module has been modeled and compared with stack-chip (SC) implementation. Thermal analysis, including comparison against stack-chip and system-on- a-chip (SoC) is also presented. It is demonstrated that CLC technology provides significant performance advantage over conventional SiP technologies and has great impact on future system-level integration.\",\"PeriodicalId\":448890,\"journal\":{\"name\":\"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.\",\"volume\":\"35 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-03-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISQED.2003.1194736\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2003.1194736","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Electrical and thermal analysis for system-in-a package (SiP) implementation platform
This paper presents an electrical and thermal performance analysis of system-in-a-package (SiP) memory/logic implementation platform based on chip-laminate-chip (CLC) technology. Internal IO interface inside CLC module has been modeled and compared with stack-chip (SC) implementation. Thermal analysis, including comparison against stack-chip and system-on- a-chip (SoC) is also presented. It is demonstrated that CLC technology provides significant performance advantage over conventional SiP technologies and has great impact on future system-level integration.
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