Automated synthesis of mixed-mode (asynchronous and synchronous) systems

Many large scale integrated circuits and systems contain both synchronous and asynchronous subsystems (including self-timed subsystems). Examples include systems having asynchronous interfaces to busses or memories, and systems containing modules clocked by independent, locally generated clocks. This paper discusses specification and automated synthesis techniques for designing such systems. A graphical perspective of the temporal and interface constraints is provided via a timing diagram editor. The specification and synthesis techniques presented allow individual process implementations to be either synchronous, asynchronous, or combinational. We discuss factors influencing the decomposition of the overall system into sub-processes and the choice of implementation styles. Fragments of the design of a Processor Interface Board (PIB) are used to illustrate various concepts. The goal is to enable a designer to improve design quality by synergistically exploiting the advantages of both the synchronous and asynchronous design styles in a system, and to support experimentation with trade-offs in granularity and implementation strategies.