L. Kushner, G. V. Andrews, W. White, J. Delaney, M. Vernon, M. Harris, David A. Whitmire
{"title":"800mhz单片GaAs HBT伺服调制器","authors":"L. Kushner, G. V. Andrews, W. White, J. Delaney, M. Vernon, M. Harris, David A. Whitmire","doi":"10.1109/GAAS.1994.636913","DOIUrl":null,"url":null,"abstract":"An 800 MHz monolithic mixed-signal serrodyne modulator IC has been developed in GaAs/AlGaAs HBT HI/sup 2/L process optimized for digital applications. This 3/spl times/2.8 mm, 2000+ transistor chip consists of a 7-bit phase accumulator driving a vector modulator, implemented as of a pair of balanced mixers, 5-bit switched-attenuators, buffer amplifiers, and control circuits. The balanced mixer's LO leakage and 3-1 products are typically 25 dB below the carrier at the nominal operating point, with all other spurs better than -50 dBc. Over a 32 dB control range, the 5-bit switched attenuator typically achieves worst-case amplitude and phase errors of 1.5 dB and 1.5/spl deg/, respectively, from 50 to 250 MHz. This first generation chip consumes 2.5 W of dc power and clocks to speeds in excess of 925 MHz.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"113 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"An 800 MHz monolithic GaAs HBT serrodyne modulator\",\"authors\":\"L. Kushner, G. V. Andrews, W. White, J. Delaney, M. Vernon, M. Harris, David A. Whitmire\",\"doi\":\"10.1109/GAAS.1994.636913\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An 800 MHz monolithic mixed-signal serrodyne modulator IC has been developed in GaAs/AlGaAs HBT HI/sup 2/L process optimized for digital applications. This 3/spl times/2.8 mm, 2000+ transistor chip consists of a 7-bit phase accumulator driving a vector modulator, implemented as of a pair of balanced mixers, 5-bit switched-attenuators, buffer amplifiers, and control circuits. The balanced mixer's LO leakage and 3-1 products are typically 25 dB below the carrier at the nominal operating point, with all other spurs better than -50 dBc. Over a 32 dB control range, the 5-bit switched attenuator typically achieves worst-case amplitude and phase errors of 1.5 dB and 1.5/spl deg/, respectively, from 50 to 250 MHz. This first generation chip consumes 2.5 W of dc power and clocks to speeds in excess of 925 MHz.\",\"PeriodicalId\":328819,\"journal\":{\"name\":\"Proceedings of 1994 IEEE GaAs IC Symposium\",\"volume\":\"113 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-10-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 1994 IEEE GaAs IC Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/GAAS.1994.636913\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1994 IEEE GaAs IC Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GAAS.1994.636913","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An 800 MHz monolithic GaAs HBT serrodyne modulator
An 800 MHz monolithic mixed-signal serrodyne modulator IC has been developed in GaAs/AlGaAs HBT HI/sup 2/L process optimized for digital applications. This 3/spl times/2.8 mm, 2000+ transistor chip consists of a 7-bit phase accumulator driving a vector modulator, implemented as of a pair of balanced mixers, 5-bit switched-attenuators, buffer amplifiers, and control circuits. The balanced mixer's LO leakage and 3-1 products are typically 25 dB below the carrier at the nominal operating point, with all other spurs better than -50 dBc. Over a 32 dB control range, the 5-bit switched attenuator typically achieves worst-case amplitude and phase errors of 1.5 dB and 1.5/spl deg/, respectively, from 50 to 250 MHz. This first generation chip consumes 2.5 W of dc power and clocks to speeds in excess of 925 MHz.