{"title":"用于人工神经网络的ULSI架构","authors":"U. Ruckert","doi":"10.1109/EMPDP.2001.905072","DOIUrl":null,"url":null,"abstract":"Three different hardware implementations of artificial neural networks are presented. The chips are model-specific integrated circuits for neural associative memories, self-organizing feature maps and local cluster neural networks. Some of the key implementational issues are considered and especially the question of resource-efficiency is discussed.","PeriodicalId":262971,"journal":{"name":"Proceedings Ninth Euromicro Workshop on Parallel and Distributed Processing","volume":"144 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"ULSI architectures for artificial neural networks\",\"authors\":\"U. Ruckert\",\"doi\":\"10.1109/EMPDP.2001.905072\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Three different hardware implementations of artificial neural networks are presented. The chips are model-specific integrated circuits for neural associative memories, self-organizing feature maps and local cluster neural networks. Some of the key implementational issues are considered and especially the question of resource-efficiency is discussed.\",\"PeriodicalId\":262971,\"journal\":{\"name\":\"Proceedings Ninth Euromicro Workshop on Parallel and Distributed Processing\",\"volume\":\"144 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings Ninth Euromicro Workshop on Parallel and Distributed Processing\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EMPDP.2001.905072\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Ninth Euromicro Workshop on Parallel and Distributed Processing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EMPDP.2001.905072","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Three different hardware implementations of artificial neural networks are presented. The chips are model-specific integrated circuits for neural associative memories, self-organizing feature maps and local cluster neural networks. Some of the key implementational issues are considered and especially the question of resource-efficiency is discussed.
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