A 92.4dB SNDR 24kHz ΔΣ modulator consuming 352μW

This paper presents a discrete time ΔΣ modulator operating under 1V power supply. To achieve high precision under low voltage while preserve low power consumption, techniques from systematic level to circuits' level are used. On the systematic level, modulator with 4-bit quantizer is employed. The advantage is its excellent stability performance which extends input signal range near to the reference voltage. As a result the size of sampling capacitor which determines the thermal noise level is reduced. The feed-forward path is introduced to the modulator loop which bypasses input signal component and let the integrator only process quantization error signal. The integrator's swing is hence suppressed, and the design requirement of amplifier inside the integrator is relaxed. On the circuits' level, single stage amplifier with only 40dB gain is adopted to construct the first integrator. Large sampling integrator can be driven with low current consumption. In the quantizer design, traditional flash quantizer is replaced by successive approximation (SAR) quantizer. The overwhelming advantage is that the number of comparators is reduced to only one which saves power and area cost. The control of SAR employs asynchronous logic which prevents high frequency clock generation. Implemented in 0.18μm standard CMOS technology the prototype modulator achieves 92.4dB peak SNDR with only 352μW power dissipation. The total chip area is 1.66mm2 including bonding pad.