具有低电压检测能力的1.8 V电源多频数字可调片上IC振荡器

A. V. Boas, J. Soldera, A. Olmos
{"title":"具有低电压检测能力的1.8 V电源多频数字可调片上IC振荡器","authors":"A. V. Boas, J. Soldera, A. Olmos","doi":"10.1145/1016568.1016587","DOIUrl":null,"url":null,"abstract":"The design of a 1.8V power supply, multi-frequency on-chip IC oscillator with a built-in low voltage detection (LVD) circuitry is described. Since the modules share the same bandgap cell, the system includes a new bandgap isolation strategy based on wide swing cascode current mirrors to reduce noise coupling into the LVD. The IC oscillator generates four selectable clock frequencies: 4 MHz and 8 MHz from 1.8 V to 5.5 V, 12 MHz and 22 MHz from 2.7 V to 5.5 V. After fine-tuning the oscillator via digital trimming its output frequency varies less than /spl plusmn/2.5% around the target frequency over supply ranges and from -40 to 125/spl deg/C. The measured clock jitter is below 0.1% whereas the recover time from stop is 5 /spl mu/s. The low voltage detection circuit monitors the supply voltage applied to the system and generates the appropriate warning or even initiates a system shutdown before the in-circuit SoC presents malfunction. The module was implemented in a 0.5 /spl mu/m CMOS technology, occupies an area of 360/spl times/530 /spl mu/m/sup 2/ and requires no external reference or components.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A 1.8 V supply multi-frequency digitally trimmable on-chip IC oscillator with low-voltage detection capability\",\"authors\":\"A. V. Boas, J. Soldera, A. Olmos\",\"doi\":\"10.1145/1016568.1016587\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The design of a 1.8V power supply, multi-frequency on-chip IC oscillator with a built-in low voltage detection (LVD) circuitry is described. Since the modules share the same bandgap cell, the system includes a new bandgap isolation strategy based on wide swing cascode current mirrors to reduce noise coupling into the LVD. The IC oscillator generates four selectable clock frequencies: 4 MHz and 8 MHz from 1.8 V to 5.5 V, 12 MHz and 22 MHz from 2.7 V to 5.5 V. After fine-tuning the oscillator via digital trimming its output frequency varies less than /spl plusmn/2.5% around the target frequency over supply ranges and from -40 to 125/spl deg/C. The measured clock jitter is below 0.1% whereas the recover time from stop is 5 /spl mu/s. The low voltage detection circuit monitors the supply voltage applied to the system and generates the appropriate warning or even initiates a system shutdown before the in-circuit SoC presents malfunction. The module was implemented in a 0.5 /spl mu/m CMOS technology, occupies an area of 360/spl times/530 /spl mu/m/sup 2/ and requires no external reference or components.\",\"PeriodicalId\":275811,\"journal\":{\"name\":\"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)\",\"volume\":\"37 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-09-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/1016568.1016587\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1016568.1016587","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5

摘要

介绍了一种1.8V电源、内置低电压检测电路的多频片上IC振荡器的设计。由于两个模块共用同一个带隙单元,该系统采用了一种基于宽摆幅级联电流镜的带隙隔离策略,以减少LVD中的噪声耦合。IC振荡器产生四个可选的时钟频率:从1.8 V到5.5 V的4 MHz和8 MHz,从2.7 V到5.5 V的12 MHz和22 MHz。通过数字微调振荡器后,其输出频率在电源范围内的目标频率周围变化小于/spl plusmn/2.5%,范围从-40到125/spl度/C。测量到的时钟抖动低于0.1%,而从停止恢复时间为5 /spl mu/s。低压检测电路监测施加到系统的电源电压,并在电路中SoC出现故障之前产生适当的警告甚至启动系统关闭。该模块采用0.5 /spl mu/m CMOS技术实现,占地面积为360/spl倍/530 /spl mu/m/sup 2/,不需要外部参考或组件。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
A 1.8 V supply multi-frequency digitally trimmable on-chip IC oscillator with low-voltage detection capability
The design of a 1.8V power supply, multi-frequency on-chip IC oscillator with a built-in low voltage detection (LVD) circuitry is described. Since the modules share the same bandgap cell, the system includes a new bandgap isolation strategy based on wide swing cascode current mirrors to reduce noise coupling into the LVD. The IC oscillator generates four selectable clock frequencies: 4 MHz and 8 MHz from 1.8 V to 5.5 V, 12 MHz and 22 MHz from 2.7 V to 5.5 V. After fine-tuning the oscillator via digital trimming its output frequency varies less than /spl plusmn/2.5% around the target frequency over supply ranges and from -40 to 125/spl deg/C. The measured clock jitter is below 0.1% whereas the recover time from stop is 5 /spl mu/s. The low voltage detection circuit monitors the supply voltage applied to the system and generates the appropriate warning or even initiates a system shutdown before the in-circuit SoC presents malfunction. The module was implemented in a 0.5 /spl mu/m CMOS technology, occupies an area of 360/spl times/530 /spl mu/m/sup 2/ and requires no external reference or components.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
A formal software synthesis approach for embedded hard real-time systems FPGA implementation of parallel turbo-decoders Leakage power optimization in standard-cell designs A switch architecture and signal synchronization for GALS system-on-chips Accurate software performance estimation using domain classification and neural networks
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1