ESL design with RTL-verified predesigned abstract communication channels

Electronic System Level (ESL) design flow tries to handle the complexity of today's System-on-Chip design and verification. Due to this complexity, design and verification methodologies start from an abstraction level higher than Register Transfer Level (RTL). In ESL, verification becomes a major bottleneck in the design flow, and finding a good verification methodology at this abstraction level is important. In this paper, we focus on communication parts of ESL designs rather than the computation parts. Here, we propose a new environment for ESL designs called RTL+, which is an abstraction level higher than RTL and yet lower than TLM-2 implementation of ESL. For RTL+ models verification, we propose using a simulation-based toolkit named C++TESK.