基于可编程芯片平台的系统功率估计工具(仅摘要)

S. Rethinagiri, Oscar Palomar, A. Cristal, O. Unsal
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引用次数: 0

摘要

不断增加的应用程序复杂性导致了耗电处理器的开发。在设计流程的早期阶段,很少有独立的工具能够很好地在估计速度和准确性之间进行权衡,以估计功率/能量。很少有工具能够解决基于电力和能源的设计空间探索问题。在本文中,我们提出了一个基于虚拟平台的独立的可编程芯片系统(SoPC)嵌入式平台的功耗和能量估计工具,它独立于内部工具。这个工具的开发涉及两个步骤。第一步是功率模型生成。对于功率模型的开发,我们使用功能参数建立了系统不同部分的通用功率模型。这是一次性的活动。在第二步中,开发了基于仿真的虚拟平台框架,以准确评估第一步中开发的相关功率模型中使用的活动。这两个步骤的结合导致了混合功率估计,它在精度和速度之间提供了更好的权衡。提出的工具有几个好处:它从整体上考虑嵌入式系统的功耗,并在没有昂贵和复杂材料的情况下进行准确的估计。该工具还可扩展,用于探索复杂的嵌入式多核体系结构。我们提出的工具的有效性通过围绕FPGA板设计的双核RISC处理器进行验证,并扩展到适应未来的多核处理器,以实现可靠的基于能源的设计空间探索。我们提出的工具的准确性通过使用各种工业基准,如多媒体,EEMBC和SPEC2006进行评估。估计的功率值与实际电路板测量值以及McPAT进行比较。我们获得的功率/能量估计结果为基于异构MPSoC的系统提供小于9%的误差,与其他最先进的功率估计工具相比,速度快200%。
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Power estimation tool for system on programmable chip based platforms (abstract only)
The ever increasing complexity of the applications result in the development of power hungry processors. There is a scarcity of standalone tools that have a good trade off between estimation speed and accuracy to estimate power/energy at an earlier phase of design flow. There are very few tools that addresses the design space exploration issue based on power and energy. In this paper, we propose a virtual platform based standalone power and energy estimation tool for System-on-Programmable Chip (SoPC) embedded platforms, which is independent of in-house tools. There are two steps involved in this tool development. The first step is power model generation. For the power model development, we used functional parameters to set up generic power models for the different parts of the system. This is a onetime activity. In the second step, a simulation based virtual platform framework is developed to evaluate accurately the activities used in the related power models developed in the first step. The combination of the two steps lead to a hybrid power estimation, which gives a better trade-off between accuracy and speed. The proposed tool has several benefits: it considers the power consumption of the embedded system in its entirety and leads to accurate estimates without a costly and complex material. The proposed tool is also scalable for exploring complex embedded multi-core architectures. The effectiveness of our proposed tool is validated through dualcore RISC processor designed around the FPGA board and extended to accommodate futuristic multi-core processors for a reliable energy based design space exploration. The accuracy of our proposed tool is evaluated by using a variety of industrial benchmarks such as Multimedia, EEMBC and SPEC2006. Estimated power values are compared to real board measurements and also to McPAT. Our obtained power/energy estimation results provide less than 9% of error for heterogeneous MPSoC based system and are 200% faster compared to other state-of-the-art power estimation tools.
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