C. Brennan, J. Kozhaya, R. Proctor, J. Sloan, Shunhua Chang, J. Sundquist, T. Lowe
{"title":"用于90nm ASIC设计系统的ESD设计自动化","authors":"C. Brennan, J. Kozhaya, R. Proctor, J. Sloan, Shunhua Chang, J. Sundquist, T. Lowe","doi":"10.1109/EOSESD.2004.5272614","DOIUrl":null,"url":null,"abstract":"Design tools for ESD are described that ensure robust protection at both the cell and chip level in a high-volume, highly automated ASIC design system. There are three primary components: Design Rule Checking (DRC) for ESD; transient CDM simulations on extracted netlists; and analysis of chip-level power supply net resistances.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"56 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":"{\"title\":\"ESD design automation for a 90nm ASIC design system\",\"authors\":\"C. Brennan, J. Kozhaya, R. Proctor, J. Sloan, Shunhua Chang, J. Sundquist, T. Lowe\",\"doi\":\"10.1109/EOSESD.2004.5272614\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Design tools for ESD are described that ensure robust protection at both the cell and chip level in a high-volume, highly automated ASIC design system. There are three primary components: Design Rule Checking (DRC) for ESD; transient CDM simulations on extracted netlists; and analysis of chip-level power supply net resistances.\",\"PeriodicalId\":302866,\"journal\":{\"name\":\"2004 Electrical Overstress/Electrostatic Discharge Symposium\",\"volume\":\"56 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"13\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 Electrical Overstress/Electrostatic Discharge Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EOSESD.2004.5272614\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 Electrical Overstress/Electrostatic Discharge Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EOSESD.2004.5272614","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
ESD design automation for a 90nm ASIC design system
Design tools for ESD are described that ensure robust protection at both the cell and chip level in a high-volume, highly automated ASIC design system. There are three primary components: Design Rule Checking (DRC) for ESD; transient CDM simulations on extracted netlists; and analysis of chip-level power supply net resistances.
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