{"title":"二维离散余弦变换的位串行VLSI结构","authors":"Anna Tatsaki, Costas Goutis","doi":"10.1016/0165-6074(94)90050-7","DOIUrl":null,"url":null,"abstract":"<div><p>In this paper, a VLSI architecture for the computation of the 2-D <em>N</em> × <em>N</em>-point Discrete Cosine Transform (DCT) is presented, where <em>N</em> is a power of 2. The proposed bit-serial architecture has highly regular structure and exhibits high data throughput rate. It is based on a high performance application specific multiplier. A chip was designed for the computation of the 4 × 4-point DCT exhibiting a performance of 246 <em>M</em><em>pixels/sec.</em></p></div>","PeriodicalId":100927,"journal":{"name":"Microprocessing and Microprogramming","volume":"40 10","pages":"Pages 829-832"},"PeriodicalIF":0.0000,"publicationDate":"1994-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/0165-6074(94)90050-7","citationCount":"0","resultStr":"{\"title\":\"A bit-serial VLSI architecture for the 2-D discrete cosine transform\",\"authors\":\"Anna Tatsaki, Costas Goutis\",\"doi\":\"10.1016/0165-6074(94)90050-7\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>In this paper, a VLSI architecture for the computation of the 2-D <em>N</em> × <em>N</em>-point Discrete Cosine Transform (DCT) is presented, where <em>N</em> is a power of 2. The proposed bit-serial architecture has highly regular structure and exhibits high data throughput rate. It is based on a high performance application specific multiplier. A chip was designed for the computation of the 4 × 4-point DCT exhibiting a performance of 246 <em>M</em><em>pixels/sec.</em></p></div>\",\"PeriodicalId\":100927,\"journal\":{\"name\":\"Microprocessing and Microprogramming\",\"volume\":\"40 10\",\"pages\":\"Pages 829-832\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://sci-hub-pdf.com/10.1016/0165-6074(94)90050-7\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microprocessing and Microprogramming\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/0165607494900507\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microprocessing and Microprogramming","FirstCategoryId":"1085","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/0165607494900507","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A bit-serial VLSI architecture for the 2-D discrete cosine transform
In this paper, a VLSI architecture for the computation of the 2-D N × N-point Discrete Cosine Transform (DCT) is presented, where N is a power of 2. The proposed bit-serial architecture has highly regular structure and exhibits high data throughput rate. It is based on a high performance application specific multiplier. A chip was designed for the computation of the 4 × 4-point DCT exhibiting a performance of 246 Mpixels/sec.
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