Study and Analysis of Leakage current and leakage power in 1T1C DRAM at Nano Scale Technology

As the variation in technology occurs, the size of the electronics gadget reduces day by day. With the downscaling of electronics device supply voltage, operating frequency, speed, and density of cells also change accordingly. Dynamic random access memory is mostly preferred for storing information in the microcomputer system due to its low latency and high-density attributes. The basic one-bit dynamic random access memory consists of an MOS transistor and a storage capacitor. Scaling reduces lateral dimensions of nMOS transistor to increase chip density per unit area on a silicon wafer. Scaling in MOS transistor is to increase the leakage in mos device which affects the performance of the system abruptly and the probability of loss of information increases. In this article, leakage current and leakage power analysis for 1T1C DRAM cell structure has been carried out for nanoscale memory devices. This paper investigates the design of a 1T1C DRAM cell at 180nm technology using cadence tool. The intention of this paper is to analyzed leakage current and power dissipation in 1T1C DRAM cell by variation of the parameter value. With a variety of capacitor value, leakage current and leakage power also reduce correspondingly. Similarly, with variation in bit line voltage, leakage current, and leakage power increase.