{"title":"分布式环境下的故障仿真","authors":"P. Duba, R. Roy, J. Abraham, W. A. Rogers","doi":"10.1109/DAC.1988.14843","DOIUrl":null,"url":null,"abstract":"Fault simulation of VLSI circuits takes considerable computing resources and there have been significant efforts to speed up the fault simulation process. A distributed fault simulator implemented on a loosely-coupled network of general-purpose computers is described. The techniques used result in a close to linear speedup and can be used effectively in most industrial VLSI CAD (computer-aided design) environments.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"81 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"43","resultStr":"{\"title\":\"Fault simulation in a distributed environment\",\"authors\":\"P. Duba, R. Roy, J. Abraham, W. A. Rogers\",\"doi\":\"10.1109/DAC.1988.14843\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Fault simulation of VLSI circuits takes considerable computing resources and there have been significant efforts to speed up the fault simulation process. A distributed fault simulator implemented on a loosely-coupled network of general-purpose computers is described. The techniques used result in a close to linear speedup and can be used effectively in most industrial VLSI CAD (computer-aided design) environments.<<ETX>>\",\"PeriodicalId\":230716,\"journal\":{\"name\":\"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.\",\"volume\":\"81 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"43\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DAC.1988.14843\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DAC.1988.14843","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Fault simulation of VLSI circuits takes considerable computing resources and there have been significant efforts to speed up the fault simulation process. A distributed fault simulator implemented on a loosely-coupled network of general-purpose computers is described. The techniques used result in a close to linear speedup and can be used effectively in most industrial VLSI CAD (computer-aided design) environments.<>
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