部分可编程电路设计

Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014) Pub Date : 2014-09-01 DOI:10.1109/EWDTS.2014.7027067

A. Matrosova, S. Ostanin, I. Kirienko, Virendra Singh

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引用次数: 3

摘要

提出了一种局部可编程电路设计的新方法，该方法可以屏蔽逻辑电路的任意门故障。假定只有一个门可能有故障。存在基于lut(查找表)的保留块clb(可配置逻辑块)，它们可能掩盖门故障。与目前使用的方法相比，建议的方法可以掩盖任何栅极故障，但不能掩盖栅极上的某些卡在故障。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Partially programmable circuit design

The new approach to partially programmable circuit design that allows masking arbitrary gate faults of a logical circuit is considered. It is supposed that only one gate may be fault. There are reserved blocks CLBs (configurable logic block) based on LUTs (Look up table) that may mask the gate fault. The suggested approach in comparison with the currently in use ones allows masking any gate fault but not the certain stuck-at faults at the gate poles.

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Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)

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