{"title":"超低功耗应用的无结复合晶体管","authors":"Anand Kumar, M. Parihar, A. Kranti","doi":"10.1109/INEC.2014.7460447","DOIUrl":null,"url":null,"abstract":"In this work, we investigate the behavior of an Ultra Low Power (ULP) composite transistor in conventional inversion mode (INV) and junctionless (JL) topologies. JL ULP transistor shows enhanced on-to-off current ratio and lower leakage current at elevated temperatures. JL ULP inverter designed with composite transistor shows enhanced noise margin. The work demonstrates new opportunities for realizing future ULP circuits with junctionless transistor.","PeriodicalId":188668,"journal":{"name":"2014 IEEE International Nanoelectronics Conference (INEC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Junctionless composite transistor for Ultra Low Power applications\",\"authors\":\"Anand Kumar, M. Parihar, A. Kranti\",\"doi\":\"10.1109/INEC.2014.7460447\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work, we investigate the behavior of an Ultra Low Power (ULP) composite transistor in conventional inversion mode (INV) and junctionless (JL) topologies. JL ULP transistor shows enhanced on-to-off current ratio and lower leakage current at elevated temperatures. JL ULP inverter designed with composite transistor shows enhanced noise margin. The work demonstrates new opportunities for realizing future ULP circuits with junctionless transistor.\",\"PeriodicalId\":188668,\"journal\":{\"name\":\"2014 IEEE International Nanoelectronics Conference (INEC)\",\"volume\":\"33 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-07-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 IEEE International Nanoelectronics Conference (INEC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/INEC.2014.7460447\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE International Nanoelectronics Conference (INEC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/INEC.2014.7460447","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Junctionless composite transistor for Ultra Low Power applications
In this work, we investigate the behavior of an Ultra Low Power (ULP) composite transistor in conventional inversion mode (INV) and junctionless (JL) topologies. JL ULP transistor shows enhanced on-to-off current ratio and lower leakage current at elevated temperatures. JL ULP inverter designed with composite transistor shows enhanced noise margin. The work demonstrates new opportunities for realizing future ULP circuits with junctionless transistor.