软件支持的设计可见性增强,用于故障分析过程改进

Chia-Chih Yen, Shen-Tien Lin, Kai Yang, Jerome Peillat, Paul Gibson, E. Auvray
{"title":"软件支持的设计可见性增强,用于故障分析过程改进","authors":"Chia-Chih Yen, Shen-Tien Lin, Kai Yang, Jerome Peillat, Paul Gibson, E. Auvray","doi":"10.1109/VDAT.2009.5158126","DOIUrl":null,"url":null,"abstract":"Traditional failure analysis (FA) process proceeds by investigating the tester results of several suspected silicon signals, and then applying CAD tools to navigate and compare pre-silicon design behaviors. However, existing CAD tools usually lack of design visibility due to the imperfect link between test and design environments. In this paper, we introduce a series of design visibility enhancement tools to augment FA process flow. These tools not only feature design comprehension and logic tracing capability, but also expand and correlate silicon data to design functionality. With the seamless visibility enhancement environment, we show the FA process can be performed more efficiently.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Software-enabled design visibility enhancement for failure analysis process improvement\",\"authors\":\"Chia-Chih Yen, Shen-Tien Lin, Kai Yang, Jerome Peillat, Paul Gibson, E. Auvray\",\"doi\":\"10.1109/VDAT.2009.5158126\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Traditional failure analysis (FA) process proceeds by investigating the tester results of several suspected silicon signals, and then applying CAD tools to navigate and compare pre-silicon design behaviors. However, existing CAD tools usually lack of design visibility due to the imperfect link between test and design environments. In this paper, we introduce a series of design visibility enhancement tools to augment FA process flow. These tools not only feature design comprehension and logic tracing capability, but also expand and correlate silicon data to design functionality. With the seamless visibility enhancement environment, we show the FA process can be performed more efficiently.\",\"PeriodicalId\":246670,\"journal\":{\"name\":\"2009 International Symposium on VLSI Design, Automation and Test\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-04-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 International Symposium on VLSI Design, Automation and Test\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VDAT.2009.5158126\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Symposium on VLSI Design, Automation and Test","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VDAT.2009.5158126","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

摘要

传统的失效分析(FA)过程是通过调查几个可疑的硅信号的测试结果,然后应用CAD工具来导航和比较硅之前的设计行为。然而,由于测试和设计环境之间的联系不完善,现有的CAD工具通常缺乏设计可见性。在本文中,我们介绍了一系列的设计可见性增强工具来增强FA流程。这些工具不仅具有设计理解和逻辑跟踪能力,而且还扩展和关联硅数据到设计功能。通过无缝可见性增强环境,我们可以更有效地执行FA过程。
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Software-enabled design visibility enhancement for failure analysis process improvement
Traditional failure analysis (FA) process proceeds by investigating the tester results of several suspected silicon signals, and then applying CAD tools to navigate and compare pre-silicon design behaviors. However, existing CAD tools usually lack of design visibility due to the imperfect link between test and design environments. In this paper, we introduce a series of design visibility enhancement tools to augment FA process flow. These tools not only feature design comprehension and logic tracing capability, but also expand and correlate silicon data to design functionality. With the seamless visibility enhancement environment, we show the FA process can be performed more efficiently.
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