Sushmita Kumari, B. Kaur, D. Vaithiyanathan, A. Mishra
{"title":"基于对称锁存器设计的低功率感测放大器触发器的分析与实现","authors":"Sushmita Kumari, B. Kaur, D. Vaithiyanathan, A. Mishra","doi":"10.1109/GCAT55367.2022.9972071","DOIUrl":null,"url":null,"abstract":"In this paper, sense amplifier based flip flop (SAFF) with different latch designs is implemented and analyzed with respect to minimum voltage supply, delay and power. The conventional SAFF along with Power PC Master Slave flip flop (MSFF) and Pulse triggered flip flop (PTFF) are also discussed. In the result section, the output waveform and parametric analysis of all the SAFFs are implemented and results of comparison of each schematic are also discussed. The schematic of all the flip flops are designed using gdpk90nm and simulated using cadence tool.","PeriodicalId":133597,"journal":{"name":"2022 IEEE 3rd Global Conference for Advancement in Technology (GCAT)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Analysis and Implementation of a Low Power Sense Amplifier based flip flop with symmetric latch design\",\"authors\":\"Sushmita Kumari, B. Kaur, D. Vaithiyanathan, A. Mishra\",\"doi\":\"10.1109/GCAT55367.2022.9972071\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, sense amplifier based flip flop (SAFF) with different latch designs is implemented and analyzed with respect to minimum voltage supply, delay and power. The conventional SAFF along with Power PC Master Slave flip flop (MSFF) and Pulse triggered flip flop (PTFF) are also discussed. In the result section, the output waveform and parametric analysis of all the SAFFs are implemented and results of comparison of each schematic are also discussed. The schematic of all the flip flops are designed using gdpk90nm and simulated using cadence tool.\",\"PeriodicalId\":133597,\"journal\":{\"name\":\"2022 IEEE 3rd Global Conference for Advancement in Technology (GCAT)\",\"volume\":\"33 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-10-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE 3rd Global Conference for Advancement in Technology (GCAT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/GCAT55367.2022.9972071\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE 3rd Global Conference for Advancement in Technology (GCAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GCAT55367.2022.9972071","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Analysis and Implementation of a Low Power Sense Amplifier based flip flop with symmetric latch design
In this paper, sense amplifier based flip flop (SAFF) with different latch designs is implemented and analyzed with respect to minimum voltage supply, delay and power. The conventional SAFF along with Power PC Master Slave flip flop (MSFF) and Pulse triggered flip flop (PTFF) are also discussed. In the result section, the output waveform and parametric analysis of all the SAFFs are implemented and results of comparison of each schematic are also discussed. The schematic of all the flip flops are designed using gdpk90nm and simulated using cadence tool.
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