Jyh-Neng Yang, Chen-Yi Lee, Terng-Yin Hsu, Terng-Ren Hsu, Chung-Cheng Wang
{"title":"一个1.5 v, 2.4GHz CMOS低噪声放大器","authors":"Jyh-Neng Yang, Chen-Yi Lee, Terng-Yin Hsu, Terng-Ren Hsu, Chung-Cheng Wang","doi":"10.1109/MWSCAS.2000.952926","DOIUrl":null,"url":null,"abstract":"A 2.4 GHz low noise amplifier has been designed in a standard CMOS 0.35 um process. The transistor model is Bsim3 for 0.35 um process. The amplifier provides a forward gain of 33 dB with a noise figure only 0.92 dB while drawing 17 mw from a 1.5 V supply. Design simulation results are presented in this paper.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A 1.5-V, 2.4GHz CMOS low-noise amplifier\",\"authors\":\"Jyh-Neng Yang, Chen-Yi Lee, Terng-Yin Hsu, Terng-Ren Hsu, Chung-Cheng Wang\",\"doi\":\"10.1109/MWSCAS.2000.952926\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 2.4 GHz low noise amplifier has been designed in a standard CMOS 0.35 um process. The transistor model is Bsim3 for 0.35 um process. The amplifier provides a forward gain of 33 dB with a noise figure only 0.92 dB while drawing 17 mw from a 1.5 V supply. Design simulation results are presented in this paper.\",\"PeriodicalId\":437349,\"journal\":{\"name\":\"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-08-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2000.952926\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2000.952926","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 2.4 GHz low noise amplifier has been designed in a standard CMOS 0.35 um process. The transistor model is Bsim3 for 0.35 um process. The amplifier provides a forward gain of 33 dB with a noise figure only 0.92 dB while drawing 17 mw from a 1.5 V supply. Design simulation results are presented in this paper.