A Ghz Mos Adaptive Pipeline Technique Using Variable Delay Circuits

Introduction Two major obstacles are encountered in the production of practical GHz synchronous LSIs. The first is the excessive design margin that must be considered in trying to efficiently accommodate both deviations in circuit delay and clock skew: designers must consider not only the deviation in device parameters but also tlie variation in such operating-environmental factors as temperature, supply voltage, etc. The second major obstacle encountered is excessive power dissipation produced by high frequency LSIs as a result of tlie fact that all of their gates are operated at a single frequency determined on the basis of the critical path propagation delay time in just o n e of the pipeline stages, which has the niaximum critical path length. The delay time of the gates in each pipeline stage does not need to be tlie same. This waste of power needs to be eliminated. This paper presents an adaptive pipeline (APL) teclinique which automatically compensates for clock skew and which avoids the necessity of including as design factors either device parameter deviations or operating-environment variations. Further, by individually controlling gate delay for each pipeline stage, the APL technique is able to eliminate excessive power dissipation. In the APL technique, MOS current mode logic (MCML)[l] is used for the low noise and variable delay fundamental logic circuits. Tlie APL is here applied to a 0.4pni MOS 1.W lGHz G4bit double-stage pipeline adder.