{"title":"用于计算机通信的250mb /s 10通道CMOS光接收机阵列设计","authors":"Kwangoh Kim, Jungryoul Choi, Joongho Choi","doi":"10.1109/APASIC.1999.824020","DOIUrl":null,"url":null,"abstract":"This paper describes design of 250 Mbps 10-channel CMOS optical receiver array for computer communication using the general-purpose CMOS technology. It is one of the most important building blocks for parallel optical interconnection system. The receiver array consists of the photo-detectors, amplifier chains and phase-locked loop for data recovery. The chip was fabricated in a 0.65 /spl mu/m 2-poly, 2-metal CMOS technology and dissipates 330 mW for one-channel and 70 mW for PLL for /spl plusmn/2.5 v supply.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Design of 250 Mb/s 10-channel CMOS optical receiver array for computer communication\",\"authors\":\"Kwangoh Kim, Jungryoul Choi, Joongho Choi\",\"doi\":\"10.1109/APASIC.1999.824020\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes design of 250 Mbps 10-channel CMOS optical receiver array for computer communication using the general-purpose CMOS technology. It is one of the most important building blocks for parallel optical interconnection system. The receiver array consists of the photo-detectors, amplifier chains and phase-locked loop for data recovery. The chip was fabricated in a 0.65 /spl mu/m 2-poly, 2-metal CMOS technology and dissipates 330 mW for one-channel and 70 mW for PLL for /spl plusmn/2.5 v supply.\",\"PeriodicalId\":346808,\"journal\":{\"name\":\"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-08-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APASIC.1999.824020\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APASIC.1999.824020","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of 250 Mb/s 10-channel CMOS optical receiver array for computer communication
This paper describes design of 250 Mbps 10-channel CMOS optical receiver array for computer communication using the general-purpose CMOS technology. It is one of the most important building blocks for parallel optical interconnection system. The receiver array consists of the photo-detectors, amplifier chains and phase-locked loop for data recovery. The chip was fabricated in a 0.65 /spl mu/m 2-poly, 2-metal CMOS technology and dissipates 330 mW for one-channel and 70 mW for PLL for /spl plusmn/2.5 v supply.
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