Prospects of ultra-thin nanowire gated 2D-FETs for next-generation CMOS technology

Although 2D semiconductor based FETs have been predicted to be very promising for the ultimate scaling (sub-10 nm nodes) of CMOS technology [1],[2], they face two major challenges in the pathway to commercialization. One is the growth of ultra-thin and high-quality gate dielectrics (preferably high-k) on top of the pristine surfaces of 2D semiconductors, which is a fundamentally difficult task. The other involves formation of ultra-short channel/gate using advanced lithography techniques, which are, however, usually expensive and/or of low yield. Using synthesized ultra-thin core/shell nanowire to gate the 2D semiconductors could be a promising approach, which not only facilitates a lithography-free ultra-short channel formation with relative ease, but also avoids the direct growth of dielectrics on 2D materials, which can help preserve the pristine nature of the 2D channel and its outstanding properties. In this work, aided by rigorous quantum simulations, we attempt to understand and optimize this nonconventional FET structure, guided by a prototype demonstration of this device. It is found that this unique FET structure offers 2D semiconductors a promising platform, in terms of manufacturability and device performance, for next-generation CMOS technology.