三维芯片堆叠技术的成品率和成本建模

IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI:10.1109/CICC.2006.320948

P. Mercier, S. R. Singh, K. Iniewski, B. Moore, P. O'Shea

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引用次数: 32

摘要

已经证明，将一组已知的好骰子堆叠到3D芯片阵列中可能有利于系统性能和占地面积。本文表明，从成品率和成本的角度来看，在一般意义上，将芯片排列成三维堆叠也是有益的。结果表明，通过将适当数量的骰子堆叠到单个系统中，会出现成本最小的最优点

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Yield and Cost Modeling for 3D Chip Stack Technologies

It has been shown that stacking a set of known good dice into a 3D chip array may be beneficial in terms of system performance and footprint area. This paper demonstrates that, in the general sense, it is also beneficial to arrange chips into a 3D stack from yield and cost perspectives. It is shown that an optimal point occurs where cost is minimized by stacking an appropriate amount of dice into a single system

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IEEE Custom Integrated Circuits Conference 2006

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