Chih-Chang Lin, Kuang-Chien Chen, M. Marek-Sadowska
{"title":"工程变更的逻辑综合","authors":"Chih-Chang Lin, Kuang-Chien Chen, M. Marek-Sadowska","doi":"10.1145/217474.217604","DOIUrl":null,"url":null,"abstract":"In the process of VLSI design, specifications are often changed. It is desirable that such changes will not lead to a very different design so that a large part of engineering effort can be preserved. We consider synthesis algorithms for handling such engineering changes. Given a synthesized network, our algorithm modifies it minimally to realize a new specification.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"254 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"106","resultStr":"{\"title\":\"Logic Synthesis for Engineering Change\",\"authors\":\"Chih-Chang Lin, Kuang-Chien Chen, M. Marek-Sadowska\",\"doi\":\"10.1145/217474.217604\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In the process of VLSI design, specifications are often changed. It is desirable that such changes will not lead to a very different design so that a large part of engineering effort can be preserved. We consider synthesis algorithms for handling such engineering changes. Given a synthesized network, our algorithm modifies it minimally to realize a new specification.\",\"PeriodicalId\":422297,\"journal\":{\"name\":\"32nd Design Automation Conference\",\"volume\":\"254 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"106\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"32nd Design Automation Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/217474.217604\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"32nd Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/217474.217604","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In the process of VLSI design, specifications are often changed. It is desirable that such changes will not lead to a very different design so that a large part of engineering effort can be preserved. We consider synthesis algorithms for handling such engineering changes. Given a synthesized network, our algorithm modifies it minimally to realize a new specification.
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