低Vce(sat) IGBT三维缩放原理的实验验证

2016 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2016-12-01 DOI:10.1109/IEDM.2016.7838390

K. Kakushima, T. Hoshii, K. Tsutsui, A. Nakajima, S. Nishizawa, H. Wakabayashi, I. Muneta, K. Sato, T. Matsudai, W. Saito, T. Saraya, K. Itou, M. Fukui, S. Suzuki, M. Kobayashi, T. Takakura, T. Hiramoto, A. Ogura, Y. Numasawa, I. Omura, H. Ohashi, H. Iwai

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引用次数: 25

摘要

三维(3D)缩放的igbt，相对于当前的商业产品(k=1)具有3 (k=3)的缩放因子。缩放应用于横向和垂直尺寸以及栅极电压。实验证实，3D缩放igbt的导通电阻显著降低，Vce(sat)从1.70 V降至1.26 V。

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Experimental verification of a 3D scaling principle for low Vce(sat) IGBT

Three dimensionally (3D) scaled IGBTs that have a scaling factor of 3 (k=3) with respect to current commercial products (k=1) were fabricated for the first time. The scaling was applied to the lateral and vertical dimensions as well as the gate voltage. A significant decrease in ON resistance, — Vce(sat) reduction from 1.70 to 1.26 V — was experimentally confirmed for the 3D scaled IGBTs.

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2016 IEEE International Electron Devices Meeting (IEDM)

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