Comparative analysis of 8 bit Carry Skip Adder using CMOS and PTL techniques with conventional MOSFET at 32 nanometer regime

The Carry Skip Adder (CSKA) is identified by a better efficiency in the trade off between operating speed and power dissipation, as it has a very low power-delay product, near to that of a carry-look ahead adder (CLA). A CSKA consists of blocks of full adder combined together, whose schematic (i.e., combination of full adders per block) mainly affects the overall operating speed of carry skip adder. These FA blocks are interconnected through 2∶1 multiplexers. Worst case delay can be reduced with different techniques which has been proposed for full adders, this paper provides an optimization technique only for the case of constant block size to improve the speed performance. The addition operations will result in sum value and carry value. In general, addition is a process which involves two numbers which are added and carry will be generated. The addition operations will result in sum value and carry value. In this paper, the performance parameters of delay, average power, PDP and EDP are compared at different technology node.