{"title":"案例研究:一种NTSC成像系统时序门阵列设计","authors":"J. Vincent","doi":"10.1109/ASIC.1989.123214","DOIUrl":null,"url":null,"abstract":"A case study of the design of a timing generator ASIC (application-specific integrated circuit) for an NTSC-compatible imaging system is presented. The case history includes many of the classic problems in this type of design. Consideration is given to the problems of changing specifications during the design process, adding special functionality while minimizing testability enhancements, the pressure of timeliness, and the importance of thoroughly verifying every part of the design.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Case study: an NTSC imaging system timing gate array design\",\"authors\":\"J. Vincent\",\"doi\":\"10.1109/ASIC.1989.123214\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A case study of the design of a timing generator ASIC (application-specific integrated circuit) for an NTSC-compatible imaging system is presented. The case history includes many of the classic problems in this type of design. Consideration is given to the problems of changing specifications during the design process, adding special functionality while minimizing testability enhancements, the pressure of timeliness, and the importance of thoroughly verifying every part of the design.<<ETX>>\",\"PeriodicalId\":245997,\"journal\":{\"name\":\"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,\",\"volume\":\"21 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-09-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1989.123214\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1989.123214","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Case study: an NTSC imaging system timing gate array design
A case study of the design of a timing generator ASIC (application-specific integrated circuit) for an NTSC-compatible imaging system is presented. The case history includes many of the classic problems in this type of design. Consideration is given to the problems of changing specifications during the design process, adding special functionality while minimizing testability enhancements, the pressure of timeliness, and the importance of thoroughly verifying every part of the design.<>
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