130nm ASIC技术中的CDM失效模式

2004 Electrical Overstress/Electrostatic Discharge Symposium Pub Date : 2004-09-01 DOI:10.1109/EOSESD.2004.5272610

C. Brennan, J. Sloan, D. Picozzi

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引用次数: 25

摘要

研究了130nm CMOS ASIC工艺中I/O电池的CDM失效。大多数故障发生在没有连接到芯片衬垫的内部电路中。故障与I/O单元的I/O电源网络电阻有关。失效模式包括由有源电路驱动的内部节点栅氧化物断裂。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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CDM failure modes in a 130nm ASIC technology

CDM failures in I/O cells in a 130 nm CMOS ASIC technology are studied. Most failures occurred in internal circuits that were not connected to chip pads. The failures correlate to the I/O power supply network resistance at the I/O cells. Failure modes include gate oxide ruptures on internal nodes driven by active circuits.

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2004 Electrical Overstress/Electrostatic Discharge Symposium

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