使用无监督深度学习结构进行异常检测的快速硬件辅助在线学习

Khaled Alrawashdeh, C. Purdy
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引用次数: 10

摘要

深度学习算法的实时场景受到两个不太经常解决的问题的挑战。首先是数据效率低下,即该模型需要多次尝试和错误才能收敛,这使得它无法应用于实时应用。二是深度学习算法的高精度计算量,在训练和推理过程中达到较高的精度。在本文中,我们解决了这两个问题,并将我们的模型应用于FPGA在线异常检测任务。为了解决第一个问题,我们提出了深度信念网络(DBN)中对比发散算法(CD)的压缩训练模型。目标是根据自由能反馈和重构误差动态调整训练向量,从而实现更好的泛化。为了解决第二个问题,我们提出了一种混合-随机-动态定点(HSDFP)方法,该方法为FPGA提供了计算,面积和功耗大幅减少的训练环境。我们的框架使DBN结构能够在线采取行动并检测攻击。因此,网络可以有效地收集训练样本数量,避免过拟合。我们表明:(1)我们提出的方法比最先进的深度学习方法收敛得更快;(2)与CPU、GPU和16位点算法相比,FPGA实现实现了0.008ms的加速推理速度和37 G-ops/s/W的高功率效率;(3)FPGA在基准数据集:MNIST、NSL-KDD和京都数据集上也实现了95%、95.4%和97.9%的最小精度下降。
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Fast hardware assisted online learning using unsupervised deep learning structure for anomaly detection
Real-time scenarios of deep learning algorithms are challenged by two less frequently addressed issues. The first is data inefficiency i.e., the model requires several epochs of trial and error to converge which makes it impractical to be applied to real-time applications. The Second is the high precision computation load of the deep learning algorithms to achieve high accuracy during training and inference. In this paper, we address these two issues and apply our model to the task of online anomaly detection using FPGA. To address the first issue, we propose a compressed training model for the contrastive divergence algorithm (CD) in the Deep Belief Network (DBN). The goal is to dynamically adjust the training vector according to the feedback from the free energy and the reconstruction error, which allows for better generalization. To address the second issue, we propose a Hybrid-Stochastic-Dynamic-Fixed-Point (HSDFP) method, which provides training environment with high reduction in calculation, area, and power in FPGA. Our framework enables the DBN structure to take actions and detect attacks online. Thus, the network can collect efficient number of training samples and avoid overfitting. We show that (1) our proposed method converges faster than the state-of-the-art deep learning methods, (2) FPGA implementation achieves accelerated inference speed of 0.008ms and a high power efficiency of 37 G-ops/s/W compared to CPU, GPU, and 16-bit fixed-point arithmetic (3) FPGA also achieves minimal degradation in accuracy of 95%, 95.4%, and 97.9% on the benchmark datasets: MNIST, NSL-KDD, and Kyoto datasets.
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