{"title":"将指令集模拟器集成到SystemC高级模型中","authors":"Ilia Oussorov, W. Raab, J. Hachmann, A. Kravtsov","doi":"10.1109/DSD.2002.1115360","DOIUrl":null,"url":null,"abstract":"This paper discusses the integration of instruction set simulators (ISS) for processor cores into highlevel system models. The approaches to providing data communication between high level modules and ISS are addressed as well as the synchronization between these parts.","PeriodicalId":330609,"journal":{"name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"Integration of instruction set simulators into SystemC high level models\",\"authors\":\"Ilia Oussorov, W. Raab, J. Hachmann, A. Kravtsov\",\"doi\":\"10.1109/DSD.2002.1115360\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper discusses the integration of instruction set simulators (ISS) for processor cores into highlevel system models. The approaches to providing data communication between high level modules and ISS are addressed as well as the synchronization between these parts.\",\"PeriodicalId\":330609,\"journal\":{\"name\":\"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-09-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DSD.2002.1115360\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DSD.2002.1115360","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Integration of instruction set simulators into SystemC high level models
This paper discusses the integration of instruction set simulators (ISS) for processor cores into highlevel system models. The approaches to providing data communication between high level modules and ISS are addressed as well as the synchronization between these parts.