Speed-Optimized Implementation of Fast Chirplet Decomposition Algorithm on FPGA-SoC

In ultrasonic nondestructive evaluation (NDE) of materials an essential step in characterizing an ultrasonic signal is decomposing the patterns of multiple interfering echoes. The Chirplet Transform (CT) is a powerful method to analyze the echoes in an ultrasonic signal. However, CT analysis is computationally heavy and impractical. Motivated by achieving real-time execution of the CT this research presents a speed-optimized implementation of the chirplet functions on FPGA. Chirplet echo generation used in Fast Chirplet Decomposition (FCD) Algorithm for ultrasonic signal analysis necessitates the frequent generation of chirplet functions with a 6-degree of freedom associated with chirplet parameters including the amplitude scaler; the time of arrival; the Gaussian envelope scaler; the phase of the chirplet; the center frequency and the frequency sweep. By minimizing the processing time of the chirplet generation, the FCD algorithm can be implemented efficiently on FPGA System-on-Chip (SoC). This study presents the hardware realization of the chirplet function on FPGA which is 37 times faster compared to using a Teensy 4.0 microcontroller, and 146 times faster than a highly popular Raspberry Pi 4.0 single board computer.